********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Jul 21, 2014
*ECN S14-1438, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiS407ADN D G S 
M1 3 GX S S PMOS W= 5865000u L= 0.3u 
M2 S GX S D NMOS W= 5865000u L= 0.41u
R1 D 3 4.718e-03 2.176e-03 1.391e-06 
CGS GX S 2.246e-09 
CGD GX D 1.440e-10 
RG G GY 3.6 
RTCV 100 S 1e6 1.890e-04 1.359e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 5865000u 
**************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 2e-8 
+ RS = 0 KP = 5.007e-06 NSUB = 9.148e+14 
+ KAPPA = 8.231e-05 NFS = 1.000e+12 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 2e-8 
+NSUB = 3.589e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 5.774e-08 TREF = 25 BV = 21 
+RS = 5.773e-02 N = 1.453e+00 IS = 6.949e-08 
+EG = 1.084e+00 XTI = -7.501e+00 TRS = 1.000e-05 
+CJO = 2.000e-11 VJ = 3.000e-01 M = 1.000e+00 ) 
.ENDS 
